1. Field of the Invention
The present invention generally relates to electronic signaling. More particularly, the present invention relates to data transmission from a first component to a second component over a signaling bus, the data transmission accompanied by one or more strobe signals normally used by the second component for the purpose of latching data received on the signaling bus.
2. Description of the Related Art
Historically, the density of circuits on silicon chips has increased exponentially and is forecasted to continue to do so for some time. “Moore's Law”, an observation by Gordon Moore, co-founder of Intel Corporation, projects that the number of transistors per square inch of silicon doubles every 18 months. Although cost of processing silicon wafers has also increased to some degree, the overwhelming density of the circuitry has dramatically reduced the cost of many electronic products, such as computers, Personal Digital Assistants (PDAs), communication devices, and the like.
In contrast to on-chip circuitry, packaging interconnections used to drive signals from a chip or to receive signals onto a chip are relatively expensive, and the number of such interconnections has not increased greatly over time. Such interconnections are called pins. In “low-cost” chip packaging, pins cost approximately 0.5 cents per pin. In “high-performance” chip packaging, used for many ASICs (Application Specific Integrated Circuits) and processors, pins cost approximately 2.0 cents per pin. Pins in memory products cost approximately 1.0 cent per pin.
As a result, many techniques have been used to reduce the number of pins required. For example, DRAMs (Dynamic Random Access Memories) have for year's time multiplexed address lines. A Row Address is transmitted by a chip such as a processor over a group of signal conductors called an address bus and is strobed into a DRAM chip by a RAS (Row Address Strobe) signal. Subsequently, a Column Address is transmitted over the same address bus and is strobed into the DRAM chip by a CAS (Column Address Strobe) signal. Use of the same signal conductors for the row address and the column address dramatically reduces the number of pins required by the DRAM chip, as well as the processor.
Although “chip” is used for simplicity in the remaining discussion, those skilled in the art will recognize that the teachings of this invention apply to interconnections at any level of packaging, including, but not limited to, multi-chip modules, printed wiring boards (PWBs), and computer enclosures. The invention applies to any electrical component coupled to another electrical component coupled by a signaling bus accompanied by one or more strobe signals.
Because signal pins need to be kept to a low number, time multiplexing data over busses is a common technique. For example, a 32-byte bus is commonly used to interconnect one chip to another. The first chip may be a processor chip; the second may be another processor chip, a chip that communicates with a memory subsystem, or an I/O (Input/Output) subsystem. Commonly, blocks of data larger than the bus width need to be transferred. For example, a 128-byte block of data would require four bus cycles, or “beats”, on the 32-byte bus for transmission. A bus cycle is the time period allocated for placing data the signal conductors of a bus and transmitting it before additional data is placed on the bus. Note that in many modern systems, another transmission begins before the previous transmission has physically reached the receiving chip. In the example, 32 bytes are transferred on a first bus cycle; 32 bytes more are transferred on a second bus cycle; 32 bytes more are transferred on a third bus cycle; and the final 32 bytes are transferred on a fourth bus cycle. Data in each bus cycle must arrive at the receiving chip within a known window of time. Such busses typically have strobe signals sent with the data to assist the receiver in determining when in the window of time the data from a particular bus cycle of data should be latched. Some busses are embodied with a single strobe for the entire bus. Some busses are embodied with a separate strobe for each byte of the bus.
The possibility of errors or malfunction on a chip or data transmission must be planned for by those designing the chip and the system in which the chip is used. Often, separate, expensive, additional busses are implemented to communicate status, errors, and diagnostics. In chips where cost is of utmost importance, and pins are kept at an absolute minimum, transmission of status, errors, and diagnostics is limited to “hard fails”, either by incorrect data being sent, or an extra (and costly) signal pin being driven to a logic level that indicates an error has occurred, with no further diagnostics being transmitted on the extra signal wire. When such an event occurs, the system utilizing the chips may be forced into a shutdown or a complex diagnostic sequence, perhaps involving scanning of chip diagnostic through LSSD (Level Sensitive Scan Design) pins.
Therefore, a need exists to transmit timely error, status, or diagnostic information without the use of additional signal conductors.